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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
ICS813252I-02
GENERAL DESCRIPTION
The ICS813252I-02 is a member of the IC S HiperClockSTM family of high performance clock HiPerClockSTM solutions from IDT. The ICS813252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClockTM frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range.
FEATURES
* Two LVPECL outputs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz * Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz * Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal * VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection * FemtoClock frequency multiplier provides low jitter, high frequency output * Absolute pull range: 50ppm * FemtoClock VCO frequency: 625MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (10kHz - 20MHz): 1.3ps (maximum) * 3.3V supply voltage * -40C to 85C ambient operating temperature
PIN ASSIGNMENT
XTAL_OUT XTAL_IN nCLK0 nCLK1 CLK0 CLK1 VCCX VCC
* Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
32 31 30 29 28 27 26 25 LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ODBSEL_1 ODBSEL_0 VCC ODASEL_1 PDSEL_2 PDSEL_1 PDSEL_0 VCCA
24 23 22 21 20 19 18 17
VEE nQB QB VCCO nQA QA VEE ODASEL_0
ICS813252I-02
32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View
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BLOCK DIAGRAM
XTAL_OUT
25MHz
ISET
LF0
LF1
XTAL_IN
Loop Filter
Output Divider
PDSEL_[2:0]
Pullup
QA nQA
CLK0 nCLK0
0
VCXO Input Pre-Divider 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440
(default)
Phase Detector
00 = 25 (default) 01 = 5 10 = 4 11 = 2
2
VCXO
Charge Pump
CLK1 nCLK1 CLK_SEL
Pulldown
FemtoClock PLL 625MHz
Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2
2
ODASEL_[1:0]
1
VCXO Feedback Divider /3125
QB nQB
VCXO Jitter Attenuation PLL
ODBSEL_[1:0]
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TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4 , 8, 1 8 , 2 4 5 6, 12, 27 7 9, 10, 11 13 14, 15 16, 17 19, 20 21 22, 23 25 26 28 29 30, 31 32 Name LF1, LF0 ISET VEE CLK_SEL VCC RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VCCA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA VCCO QB, nQB nCLK1 CLK1 nCLK0 CLK0 XTAL_OUT, XTAL_IN VCCX Type Analog Input/Output Analog Input/Output Power Input Power Reserved Input Power Input Input Output Power Output Input Input Input Input Input Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup Description Loop filter connection node pins. LF0 is the output. LF1 is the input. Charge pump current setting pin. Negative supply pins. Input clock select. When HIGH selects CLK1/nCLK1. Pulldown When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. Reserved pin. Do not connect. Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Analog supply pin. Frequency select pins for Bank B output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Differential Bank A clock outputs. LVPECL interface levels. Output power supply pin. Differential Bank B clock outputs. LVPECL interface levels. Inver ting differential clock input. VCC/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 bias voltage when left floating. Non-inver ting differential clock input. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs PDSEL_2 0 0 0 0 1 1 1 1 PDSEL_1 0 0 1 1 0 0 1 1 PDSEL_0 0 1 0 1 0 1 0 1 Pre-Divider Value 1 193 256 2430 3125 9720 15625 19440 (default)
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs ODxSEL_1 0 0 1 1 ODxSEL_0 0 1 0 1 Output Divider Value 25 (default) 5 4 2
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TABLE 3C. FREQUENCY FUNCTION TABLE
Input Frequency (MHz) 0.008 0.008 0.008 0.008 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 19.44 19.44 19.44 19.44 25 25 25 25 77.76 77.76 77.76 77.76 125 125 125 125 155.52 155.52 155.52 155.52 Pre-Divider Value 1 1 1 1 193 193 193 193 256 256 256 256 2430 2430 2430 2430 3125 3125 3125 3125 9720 9720 9720 9720 15625 15625 15625 15625 19440 19440 19440 19440 VCXO Frequency (MHz) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 FemtoClock Feedback Divider Value 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 Femtoclock VCO Frequency (MHz) 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 Output Divider Value 25 5 4 2 25 5 4 2 25 5 4 2 25 5 4 2 25 5 4 2 25 5 4 2 25 5 4 2 25 5 4 2 Output Frequency (MHz) 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5 25 125 156.25 312.5
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 37C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol VCC VCCA VCCO VCCX IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Charge Pump Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.15 3.135 3.135 Typical 3. 3 3.3 3. 3 3. 3 Maximum 3.465 VCC 3.465 3.465 235 15 Units V V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = -40C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK_SEL, ODASEL_[0:1], Input High Current ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], Input Low Current ODBSEL_[0:1] PDSEL[0:2] Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical
TO
85C
Units V V A A A A
Maximum VCC + 0.3 0.8 150 5
IIL
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TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 Units A A A V V
Peak-to-Peak Input Voltage; NOTE 1
VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol fIN fOUT Parameter Input Frequency Output Frequency RMS Phase Jitter (Random); NOTE 1 Accumulated Jitter, RMS; NOTE 2 Peak-to-Peak Jitter Output Skew; NOTE 2, 3 Output Duty Cycle Output Rise/Fall Time 20% to 80% 45 200 125MHz fOUT, 25MHz cr ystal Integration Range: 10kHz - 20MHz 125MHz fOUT, 25MHz cr ystal, 20K Cycles 100K Random Cycles Test Conditions Minimum 0.008 25 Typical Maximum 155.52 312.5 1.3 10 35 75 55 700 Units MHz MHz ps ps ps ps % ps ms
tjit(O) tjit(acc) tjit(pk-pk) tsk(o)
odc t R / tF
PLL Lock Time 175 tLOCK Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points.
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TYPICAL PHASE NOISE @ 125MHZ
125MHz
RMS Phase Jitter (Random) 10kHz to 20MHz = 0.98ps (typical)
PHASE NOISE
(dBc) HZ
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2V 2V
VCC
VCC, VCCO, VCCX VCCA
Qx
SCOPE
nCLK0, nCLK1
V
PP
Cross Points
V
CMR
LVPECL
nQx VEE
CLK0, CLK1
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Phase Noise Plot
nFOUTx
Noise Power
FOUTx
Phase Noise Mask
nFOUTy FOUTy
f1
Offset Frequency
tsk(o)
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT SKEW
nQA, nQB 80% 80% VSW I N G QA, QB 20% tR tF 20%
nQA, nQB QA, QB
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813252I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCX, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
VDD .01F VDDX .01F VDDA .01F
3.3V
10 10 10F
10F
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
2.5V
2.5V 3.3V
*R3
33
Zo = 50
Zo = 60
R3 120
R4 120
CLK Zo = 50 nCLK
CLK Zo = 60 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
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VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical performance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
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SCHEMATIC EXAMPLE
Figure 6 shows an example of the ICS813252I-02 application schematic. In this example, the device is operated at VCC = VCCX = VCCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole filter
can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used.
FIGURE 6. ICS813252I-02 SCHEMATIC EXAMPLE
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VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a cr ystal also var ies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal's CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal's CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, C S and C P values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not r un under neath the device, loop filter or crystal components.
LF0 LF1 ISET
RS
CP CS
RSET
XTAL_IN CTUNE 25MHz CTUNE XTAL_OUT
VCXO CHARACTERISTICS TABLE
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 15,700 9.9 22.2 Unit Hz/V pF pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth 10Hz (Low) 90Hz (Mid) 300Hz (High) Crystal Frequency (MHz) 25MHz 25MHz 25MHz RS (k ) 121 22 1 680 CS (F) 1.0 0.1 0.1 CP (F) 0.01 0.001 0.0001 RSET (k ) 9.09 2.21 2.21
CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO /C1 ESR Parameter Mode of Operation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25C -40 10 4 22 0 24 0 20 1 3 per year mW ppm Minimum Typical 25 20 20 85 Maximum Units MHz ppm ppm C pF pF Fundamental
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813252I-02. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 235mA = 814.275mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.874W * 37C/W = 117.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 32 LEAD VFQFN, FORCED CONVECTION
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination
voltage of V
CCO
- 2V.
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (V
CCO_MAX
-V
OH_MAX
) = 0.9V
OL_MAX
*
For logic low, VOUT = V
=V
CC_MAX
- 1.7V
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TRANSISTOR COUNT
The transistor count for ICS813252I-02 is: 6579
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PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The above mechanical package drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL N A A1 A3 b e ND NE D, E D2, E2 L 3.0 0.30 0.18 0.50 BASIC 8 8 5.0 BASIC 3.3 0.50 0.80 0 0.25 Reference 0.30 Minimum 32 1.0 0.05 Maximum
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number 813252CKI-02 813252CKI-02T 813252CKI-02LF 813252CKI-02LFT Marking ICS3252CI02 ICS3252CI02 ICS352CI02L ICS352CI02L Package 32 Lead VFQFN 32 Lead VFQFN 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN Shipping Packaging tray 2500 tape & reel tray 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A Table T9 Page 20 Description of Change Ordering Information Table - added ICS prefix in the Par t/Order Number. Date 5/6/08
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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